1. Field of the Invention
The present invention relates to a semiconductor device having a plurality of power supply circuits and a plurality of internal circuits, and more particularly to a method of testing a semiconductor device having a plurality of power supply circuits whose generated voltages are different from each other, and a plurality of internal circuits whose operating voltages are different from each other.
2. Description of the Related Art
Various semiconductor devices have found use in various fields. One example of conventional semiconductor device is a flash memory as an information storage medium.
Flash memories are capable of electrically writing and reading information. However, different voltages are required to write and read information.
Specifically, information stored in a flash memory is read under an ordinary power supply voltage. However, voltages different from the ordinary power supply voltage are needed respectively to write and erase information. For this reason, a flash memory has a plurality of power supply circuits whose generated voltages are different from each other, and a plurality of internal circuits whose operating voltages are different from each other.
One such conventional semiconductor device will be described below with reference to FIGS. 1 through 3 of the accompanying drawings.
As shown in FIG. 1, a semiconductor device 1 has a charge pump 2 as a high-voltage power supply circuit for outputting high-voltage positive electric power and a charge pump 3 as a low-voltage power supply circuit for outputting low-voltage positive electric power.
To the charge pump 2, there is connected a high-voltage internal circuit 4 which operates with high-voltage electric power. To the charge pump 3, there is connected a low-voltage internal circuit 5 which operates with low-voltage electric power.
The charge pump 2 and the internal circuit 4 are interconnected by a high-voltage power line 6a having a high-voltage power supply switch unit 8. The charge pump 3 and the internal circuit 5 are interconnected by a low-voltage power line 7a having a low-voltage power supply switch unit 9.
The power supply switch units 8, 9 have respective pairs of p-type MOS (Metal Oxide Semiconductor) transistors 10, 11 inserted in series in the respective power lines 6a, 7a. In the MOS transistors 10, 11, back gates 12 are connected in opposite directions.
Level shifters 14, 15 are connected respectively to gate electrodes 13 of the MOS transistors 10, 11 of the power supply switch units 8, 9. The level shifters 14, 15 are connected to control terminals 16, 17 of the power supply switch units 8, 9.
Each of the level shifters 14, 15 comprises a pair of p-type MOS transistors 18, 19 and a pair of n-type MOS transistors 20, 21. The MOS transistors 20, 21 of the level shifters 14, 15 are connected to the control terminals 16, 17 through inverters 22.
High- and low-voltage control lines 6b, 7b are connected respectively to junctions between the charge pumps 2, 3 and the internal circuits 4, 5. High- and low-voltage connection pads 31, 32 serving as external terminals are connected respectively to the control lines 6b, 7b.
A high-voltage external switch unit 33 is connected to the high-voltage control line 6b, and a low-voltage external switch unit 34 is connected to the low-voltage control line 7b.
The external switch units 33, 34 are identical in structure to each other, and have p-type MOS transistors 35, respectively, which serve as high- and low-voltage external switches. The MOS transistors 35 have respective back gates 12 connected to the control line 6b which in turn is connected to the power line 6a connected to the charge pump 2. The MOS transistors 35 have respective gate electrodes 13 connected to respective level shifters 36, 37.
Each of the level shifters 36, 37 comprises a pair of p-type MOS transistors 18, 19 and a pair of n-type MOS transistors 20, 21. The MOS transistors 20, 21 of the level shifters 36, 37 are connected to respective control terminals 38, 39 through inverters 22.
A control circuit (not shown) is connected to the control terminals 16, 17, 38, 39 of the switch units 8, 9, 33, 34.
The control circuit outputs a control signal "SW1" for turning on and off the power supply switch unit 8 to the control terminal 16, and outputs a control signal "SW2" for turning on and off the external switch unit 33 to the control terminal 38.
Similarly, the control circuit outputs a control signal "SW3" for turning on and off the power supply switch unit 9 to the control terminal 17, and outputs a control signal "SW4" for turning on and off the external switch unit 34 to the control terminal 39.
The control circuit has a dedicated input terminal for receiving control information from an external source for turning on and off the switch units 8, 9, 33, 34 under integrated control.
As shown in FIG. 2 of the accompanying drawings, when the semiconductor device 1 is in a normal mode of operation, the power supply switch units 8, 9 are turned on by the control circuit, and the high- and low-voltage external switch units 33, 34 are turned off by the control circuit.
At this time, electric power of different voltages are supplied from the charge pumps 2, 3 through the power supply switch units 8, 9 to the internal circuits 4, 5. Therefore, the internal circuits 4, 5 whose operating voltages are different from each other can operate normally.
The charge pumps 2, 3 and the internal circuits 4, 5 are disconnected from the connection pads 31, 32 by the switch units 33, 34. Therefore, the electric power generated by the charge pumps 2, 3 is prevented from leaking out from the connection pads 31, 32. At the same time, noise is prevented from entering the internal circuits 4, 5 from the connection pads 31, 32.
For conducting various tests on the semiconductor device 1, a testing external circuit (not shown) is connected to the connection pads 31, 32 and the input terminal of the control circuit, and the control circuit turns on and off the switch units 8, 9, 33, 34. For example, for detecting the electric power supplied from the charge pumps 2, 3 to the internal circuits 4, 5, all the switch units 8, 9, 33, 34 are turned on, as shown in FIG. 3a of the accompanying drawings.
The voltage of the electric power supplied from the high-voltage charge pump 2 to the internal circuit 4 can now be detected from the high-voltage connection pad 31, and the voltage of the electric power supplied from the low-voltage charge pump 3 to the internal circuit 5 can now be detected from the low-voltage connection pad 32.
For supplying electric power from an external power source connected to the high-voltage connection pad 31 to the internal circuits 4, 5, the power supply switch units 8, 9 are turned off and the external switch units 33, 34 are turned on.
Electric power can now be supplied from the high-voltage connection pad 31 to the internal circuit 4, and electric power can now be supplied from the low-voltage connection pad 32 to the internal circuit 5.
In the above semiconductor device 1, the charge pumps 2, 3 and the internal circuits 4, 5 correspond to positive voltages. Therefore, the various components connected to the power lines 6a, 7a and the control lines 6b, 7b are turned on and off by the p-type MOS transistors 10, 11, 35.
In the p-type MOS transistors 10, the direction of the electric power that can be turned on and off is limited because of the direction in which the back gates 12 are connected.
For example, in the external switch units 33, 34, the potentials at the junctions between the charge pumps 2, 3 and the internal circuits 4, 5 are higher than the potentials at the connection pads 31, 32 in the normal mode of operation, and the potentials at the connection pads 31, 32 are never higher.
For disconnecting the higher-potential circuits 2-5 from the lower-potential connection pads 31, 32 in the normal mode of operation, the back gates 12 of the MOS transistors 35 of the external switch units 33, 34 are connected to the lines 6b, 7b that are connected to the circuits 2-5.
If the voltages of electric power to be supplied from the connection pads 31, 32 to the internal circuits 4, 5 are higher than the voltages of electric power produced by the charge pumps 2, 3, then the electric power supplied from the external power source can well be supplied from the connection pads 31, 32 to the internal circuits 4, 5.
At this time, the MOS transistors 35 whose back gates 12 are connected to the lines 6b, 7b that are connected to the circuits 2-5 cannot turn on and off the electric power supplied from the external power source. However, no problem arises because the electric power supplied from the external power source can be turned on and off by the external power source which is connected to the connection pads 31, 32.
With respect to the power supply switches 8, 9, since higher potentials switch around in the normal and test modes of operation, it is necessary to turn on and off the supplied electric power no matter which side of the power supply switches 8, 9 the higher potentials are present on.
To meet such a requirement, the MOS transistors 10, 11 whose back gates 12 are connected in different directions are inserted in series in the power lines 6a, 7a.
In the above semiconductor device 1, the charge pumps 2, 3, the internal circuits 4, 5, and the connection pads 31, 32 can be connected in various configurations by the switch units 8, 9, 33, 34. Therefore, the semiconductor device 1 can be subject to various test modes of operation as well as the normal mode of operation.
For individually testing the two charge pumps 2, 3 and the two internal circuits 4, 5, the semiconductor device 1 has the two connection pads 31, 32. The connection pads 31, 32 are provided as terminals projecting outwardly from the semiconductor device 1. If the number of connection pads increases, then the semiconductor device 1 has an increased outer profile and needs an increased installation area.
Since the above semiconductor device 1 has the two charge pumps 2, 3 and the two internal circuits 4, 5, there are also two connection pads 31, 32. However, if the number of voltage types increases, then the number of connection pads that are required also increases, resulting in an increased semiconductor device size.